Constant fraction integer multiplication

ABSTRACT

A binary logic circuit is provided for determining a rounded value of 
               px   q     ,         
where p and q are coprime constant integers with p&lt;q and q≠2 i , i is any integer, and x is an integer variable between 0 and integer M where M≥2q, the binary logic circuit implementing in hardware the optimal solution of the multiply-add operation
 
               ax   +   b       2   k           
where a, b and k are fixed integers.

BACKGROUND

This invention relates to a logic circuit for implementing binarymultiplication by a constant fraction and to a method of deriving abinary logic circuit for performing such multiplication.

When designing integrated circuits, logic is often required to performaddition, subtraction, multiplication and division. Whilst addition,subtraction and multiplication operations can all be cheaply implementedin hardware, division is acknowledged to be an expensive operation toimplement in hardware.

In the case that the divisor is known to be a constant at design-time, adivision operation can be expressed as multiplication by a constantfraction and it is possible to construct efficient implementations ofthe division operation using a combination of addition and constantmultiplication logic. This can significantly simplify the logic andhence reduce the area of integrated circuit needed to implement thedivision operation. For example, if the division operation

$\frac{px}{q},$where p and q are integer constants and x is an integer variable, can berewritten in the form

$\frac{{ax} + b}{2^{k}},$then the division operation can be expressed in logic as a multiply-addoperation whose result is right-shifted by k binary places. However,there are an infinite number of values of a, b and k which satisfy thisequation, some of which provide less efficient expressions in logic thanothers.

US Patent Application 2013/0103733, which is incorporated by referencein its entirety, discloses techniques for deriving values for a, b and kfor use in designing integrated circuit logic, but does not describelogic optimally configured according to the most efficient expression ofmultiplication by a constant fraction. Suboptimal expressions ofdivision logic, even those embodied as a multiply-add operation, areoverly complex and consume a greater area of integrated circuit thannecessary.

BRIEF SUMMARY

According to a first aspect of the disclosure there is provided a binarylogic circuit configured to determine a rounded value of

$\frac{px}{q},$where p and q are coprime constant integers with p<q and q≠2^(i), i isany integer, and x is an integer variable between 0 and integer M whereM≥2q, the binary logic circuit being configured to implement theoperation:

$\frac{{ax} + b}{2^{k}}$where a and b are fixed integers and k is the smallest integer thatsatisfies either:

$\begin{matrix}{{\frac{2^{k}}{( {p\; 2^{k}} ){mod}\mspace{11mu} q} > {{q\lfloor \frac{M}{q} \rfloor} - q + p^{- 1}}};{or}} & (a) \\{\frac{2^{k}}{( {{- p}\; 2^{k}} ){mod}\mspace{11mu} q} > {M - ( {( {M + p^{- 1}} ){mod}\mspace{11mu} q} )}} & (b)\end{matrix}$wherein:

-   -   if (a) is satisfied by a smaller integer k than (b), then a is        an integer given by

$\lfloor \frac{p\; 2^{k}}{q} \rfloor$

-   -    and b is an integer in the range

$\lbrack {{\lfloor \frac{M}{q} \rfloor( {( {p\; 2^{k}} ){mod}\mspace{11mu} q} )},{\frac{2^{k} + {( {q - p^{- 1}} )( {( {p\; 2^{k}} ){mod}\mspace{11mu} q} )}}{q} - 1}} \rbrack;$and

-   -   if (b) is satisfied by a smaller integer k than (a), then a is        an integer given by

$\lceil \frac{p\; 2^{k}}{q} \rceil$

-   -    and b is an integer in the range

$\lbrack {0,{\frac{2^{k} - {( {M - ( {( {M + p^{- 1}} ){mod}\mspace{11mu} q} )} )( {( {{- p}\; 2^{k}} ){mod}\mspace{14mu} q} )}}{q} - 1}} \rbrack.$

The binary logic circuit may be a binary multiplier array having aplurality of rows, a first subset of the plurality of rows beingconfigured to perform multiplication by the fixed integer a, a secondsubset of the plurality of rows being configured to perform the additionof b, and said rounded value being the output of the multiplier arrayright-shifted by k binary digits.

The first subset of the plurality of rows of the binary multiplier arraymay be a substantially minimum number of rows required to implement themultiplication of x by fixed integer a.

The second subset of the plurality of rows of the binary multiplierarray may be a single row arranged to perform the addition of fixedinteger b.

The plurality of rows of the multiplier array may be arranged such thatthe representations of the integer variable x at those rows arecollectively truncated by a set of Δ least significant digits, the setof Δ least significant digits being substantially the largest number ofleast significant digits that can be discarded without causing themultiplier array to deviate from the true rounded value of

$\frac{px}{q}$for any x between 0 and M.

The fixed integer b may be the integer having the smallest Hammingweight which satisfies said operation for all x.

In the case that (a) is satisfied by a smaller integer k than (b), ifthere is more than one value of b having the same smallest Hammingweight, the fixed integer b may be the smallest value of b.

The multiplier may make use of a canonical signed digit representation.

The multiplier array may be unable to perform multiplication by avariable.

The binary logic circuit may be configured to determine the roundedvalue of

$\frac{px}{q}$according to any one of the following rounding schemes: round towardszero (RTZ), round towards negative infinity (RTN), round towardspositive infinity (RTP), and round towards nearest with ties to upper(RTU).

In embodiments, a machine readable storage medium having encoded thereonnon-transitory machine readable code can be provided for generating thebinary logic circuit.

According to a second aspect, there is provided a fixed point filtercomprising one or more binary logic circuits configured according to theteaching herein.

According to a third aspect, there is provided a method of deriving ahardware representation of a binary logic circuit configured todetermine a rounded value of

$\frac{px}{q},$where p and q are coprime constant integers with p<q and q≠2^(i), i isany integer, and x is an integer variable between 0 and integer M whereM≥2q, the method comprising:

-   -   determining an integer k being the smallest integer that        satisfies either:

$\begin{matrix}{{\frac{2^{k}}{( {p\; 2^{k}} ){mod}\mspace{11mu} q} > {{q\lfloor \frac{M}{q} \rfloor} - q + p^{- 1}}};{or}} & (a) \\{\frac{2^{k}}{( {{- p}\; 2^{k}} ){mod}\mspace{11mu} q} > {M - ( {( {M + p^{- 1}} ){mod}\mspace{11mu} q} )}} & (b)\end{matrix}$

-   -   determining fixed integers a and b where:        -   if (a) is satisfied by a smaller integer k than (b),            calculating a as the integer given by

$\lfloor \frac{p\; 2^{k}}{q} \rfloor$

-   -   -    and selecting b from the set of one or more integers in the            range

$\lbrack {{\lfloor \frac{M}{q} \rfloor( {( {p\; 2^{k}} ){mod}\mspace{11mu} q} )},{\frac{2^{k} + {( {q - p^{- 1}} )( {( {p\; 2^{k}} ){mod}\mspace{11mu} q} )}}{q} - 1}} \rbrack,$

-   -   -    and        -   if (b) is satisfied by a smaller integer k than (a),            calculating a as the integer given by

$\lceil \frac{p\; 2^{k}}{q} \rceil$

-   -   -    and selecting b from the set of one or more integers in the            range

$\lbrack {0,{\frac{2^{k} - {( {M - ( {( {M + p^{- 1}} )\mspace{11mu}{mod}\mspace{20mu} q} )} )( {( {{- p}\; 2^{k}} )\mspace{11mu}{mod}\mspace{20mu} q} )}}{q} - 1}} \rbrack;$and

-   -   deriving a hardware representation for a binary logic circuit        configured to implement the operation:

$\frac{{ax} + b}{2^{k}}$using the determined fixed integers a, b and k.

Deriving the hardware representation for the binary logic circuit maycomprise implementing said operation using a binary multiplier arrayhaving a plurality of rows, a first subset of the plurality of rowsbeing configured to perform multiplication by the fixed integer a, asecond subset of the plurality of rows being configured to perform theaddition of b, and the rounded value being the output of the multiplierarray right-shifted by k binary digits.

The method may further comprise modifying said hardware representationby truncating a set of Δ least significant digits from the plurality ofrows, the set of Δ least significant digits being substantially thelargest set of least significant digits that can be discarded withoutcausing the operation implemented by the binary logic circuit to deviatefrom the true rounded value of

$\frac{px}{q}$for any x between 0 and M.

The fixed integer b may be selected to be the integer having thesmallest Hamming weight that satisfies the truncated hardwarerepresentation for the binary logic circuit.

Deriving the hardware representation may comprise selecting a multiplierarray incapable of performing multiplication of integer x by a variablefactor.

The hardware representation may be RTL, a hardware description language,or a gate-level description language.

In embodiments, a computer readable storage medium having encodedthereon non-transitory computer readable code can be provided forgenerating a hardware representation according to the method of thethird aspect of the present invention.

According to a fourth aspect, there is provided a binary logic circuitconfigured to determine a rounded value of

$\frac{{p*x} + r}{q},$where p and q are coprime constant integers with p<q and q≠2^(i), r is apositive integer, i is any integer, and x is an integer variable betweenintegers A and B where (B−A)≥2q, the binary logic circuit beingconfigured to implement the operation:

$\frac{{ax} + b}{2^{k}}$where a and b are fixed integers and k is the smallest integer thatsatisfies either:

$\begin{matrix}{{{\frac{2^{k}}{( {p\; 2^{k}} ){mod}\mspace{14mu} q} > {\beta_{\min}^{-} - \beta_{\max}^{-}}}{where},{\beta_{\max}^{-} = {A + {( {{- A} - {P_{q}^{- 1}( {r + 1} )}} )\mspace{11mu}{mod}\mspace{14mu} q}}}}{\beta_{\min}^{-} = {B - {( {B + {r*P_{q}^{- 1}}} )\mspace{11mu}{mod}\mspace{14mu} q}}}{{or}:}} & (a) \\{{{\frac{2^{k}}{( {{- p}\; 2^{k}} )\mspace{11mu}{mod}\mspace{14mu} q} > {\beta_{\max}^{+} - \beta_{\min}^{+}}}{where},{\beta_{\max}^{+} = {B - {( {B + {P_{q}^{- 1}( {r + 1} )}} )\mspace{11mu}{mod}\mspace{14mu} q}}}}{\beta_{\min}^{+} = {A + ( {{- A} - {r*{P_{q}^{- 1}( {r + 1} )}\mspace{11mu}{mod}\mspace{14mu} q}} }}} & (b)\end{matrix}$wherein:

-   -   if (a) is satisfied by a smaller integer k than (b), then a is        an integer given by

$\lfloor \frac{p\; 2^{k}}{q} \rfloor$

-   -    and b is an integer in the range

$\lbrack {\frac{{r\; 2^{k}} + {\beta_{\min}^{-}*( {p\; 2^{k}} )\mspace{11mu}{mod}\mspace{20mu} q}}{q},{\frac{\;{{2^{k}( {r + 1} )} + {\beta_{\max}^{-}*( {p\; 2^{k}} ){mod}\mspace{20mu} q}}}{q} - 1}} \rbrack;$

-   -    and    -   if (b) is satisfied by a smaller integer k than (a), then a is        an integer given by

$\lceil \frac{p\; 2^{k}}{q} \rceil$

-   -    and b is an integer in the range

$\lbrack {\frac{{r\; 2^{k}} - {\beta_{\min}^{+}*( {{- p}\; 2^{k}} ){mod}\mspace{20mu} q}}{q},{\frac{\;{{2^{k}( {r + 1} )} - {\beta_{\max}^{+}*( {{- p}\; 2^{k}} ){mod}\mspace{20mu} q}}}{q} - 1}} \rbrack.$

According to a fifth aspect, there is provided a method of deriving ahardware representation of a binary logic circuit configured todetermine a rounded value of

$\frac{{p*x} + r}{q},$wherein p and q are coprime constant integers with p<q and q≠2^(i), r isa positive integer, i is any integer, and x is an integer variablebetween integers A and B where (B−A)≥2q, the method comprising:

-   -   determining an integer k being the smallest integer that        satisfies either:

$\begin{matrix}{{{\frac{2^{k}}{( {p\; 2^{k}} ){mod}\mspace{14mu} q} > {\beta_{\min}^{-} - \beta_{\max}^{-}}}{where},{\beta_{\max}^{-} = {A + {( {{- A} - {P_{q}^{- 1}( {r + 1} )}} )\mspace{11mu}{mod}\mspace{14mu} q}}}}{\beta_{\min}^{-} = {B - {( {B + {r*P_{q}^{- 1}}} )\mspace{11mu}{mod}\mspace{14mu} q}}}{{or}:}} & (a) \\{{{\frac{2^{k}}{( {{- p}\; 2^{k}} )\mspace{11mu}{mod}\mspace{14mu} q} > {\beta_{\max}^{+} - \beta_{\min}^{+}}}{where},{\beta_{\max}^{+} = {B - {( {B + {P_{q}^{- 1}( {r + 1} )}} )\mspace{11mu}{mod}\mspace{14mu} q}}}}{\beta_{\min}^{+} = {A + ( {{- A} - {r*{P_{q}^{- 1}( {r + 1} )}\mspace{11mu}{mod}\mspace{14mu} q}} }}} & (b)\end{matrix}$

-   -   determining fixed integers a and b where:        -   if (a) is satisfied by a smaller integer k than (b),            calculating a as the integer given by

$\lfloor \frac{p\; 2^{k}}{q} \rfloor$

-   -   -    and selecting b from the set of one or more integers in the            range

$\lbrack {\frac{{r\; 2^{k}} + {\beta_{\min}^{-}*( {p\; 2^{k}} ){mod}\mspace{14mu} q}}{q},{\frac{\;{{2^{k}( {r + 1} )} + {\beta_{\max}^{-}*( {p\; 2^{k}} ){mod}\mspace{14mu} q}}}{q} - 1}} \rbrack,$

-   -   -    and        -   if (b) is satisfied by a smaller integer k than (a),            calculating a as the integer given by

$\lceil \frac{p\; 2^{k}}{q} \rceil$

-   -   -    and selecting b from the set of one or more integers in the            range

$\lbrack {\frac{{r\; 2^{k}} - {\beta_{\min}^{+}*( {{- p}\; 2^{k}} ){mod}\mspace{14mu} q}}{q},{\frac{{2^{k}( {r + 1} )} - {\beta_{\max}^{+}*( {{- p}\; 2^{k}} ){mod}\mspace{14mu} q}}{q} - 1}} \rbrack;$and

-   -   deriving a hardware representation for a binary logic circuit        configured to implement the operation:

$\frac{{ax} + b}{2^{k}}$using the determined fixed integers a, b and k.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the disclosure will now be explained by way of example withreference to the accompanying drawings. In the drawings:

FIG. 1 is a schematic illustration of the multiply, add and shiftoperations performed by a multiplication array and adder unit inaccordance with the examples described herein.

FIG. 2 is an illustration of a solution space.

FIG. 3 illustrates the advantages of implementing multiplication by aconstant fraction using a 40 nm process according to the principlestaught herein.

FIG. 4 illustrates a fixed point multiplication array from which a setof least significant binary digits Δ are removed.

FIG. 5 is a schematic diagram of a fixed point filter.

FIG. 6 is a schematic diagram of a logic circuit configured inaccordance with the principles described herein.

FIG. 7 is a flowchart illustrating a method according to the principlesdescribed herein.

DETAILED DESCRIPTION

The following description is presented by way of example to enable anyperson skilled in the art to make and use implementations of thedisclosure. Implementations are not limited to the embodiments describedherein and various modifications to the disclosed embodiments will bereadily apparent to those skilled in the art.

There is a need for improved integrated circuit logic implementingmultiplication by a constant fraction as a multiply-add operation in itsmost efficient form.

Consider the operation

$\frac{px}{q},$where p and q are integer constants and x is an integer variable. Such amultiplication by a constant fraction is common in hardwareimplementations of fixed point filters, for example:y= 1/7a+ 2/7bt+ 3/7ct ²+ 1/7dt ³

In this example, the fixed point filter requires division by a constantdivisor of 7. Conventionally such an operation would be implementedusing complex logic designed for non-constant division, but asignificant reduction in hardware complexity can be achieved byexpressing the operation in the form

$\frac{{ax} + b}{2^{k}},$which represents a multiply-add operation whose result is right-shiftedby k binary places.

A fixed point filter 501 configured in accordance with the presentexample is shown in FIG. 5. The filter receives an input value t andprovides an output value y at a predetermined level of precision. Thefilter 501 comprises multiply-add logic 502 for performingmultiplication by the constant fractions 1/7, 2/7 and 3/7 as required bythe filter. These operations could be performed by one or more sets ofmultiply-add logic 502 each configured to perform multiplication by afraction having a constant divisor of 7.

For fixed point operations, the multiplication by a constant fractionoperation to be performed is:

${Round}( \frac{px}{q} )$where round is performed according to the selected rounding scheme forthe system concerned. Rounding schemes include, for example, roundtowards zero (RTZ), round towards negative infinity (RTN), round towardspositive infinity (RTP), and round towards nearest with ties to upper(RTU). In the above operation, p and q are natural numbers and x is apositive integer between 0 and M. The following mathematical analysisalso assumes that p and q are coprime constants and that:p<q q≠2^(i) M≥2q

With a round towards negative infinity (RTN) or round towards zero (RTZ)scheme, the multiplication by a constant fraction operation can beexpressed as the floor of a multiply-add operation:

$\lfloor \frac{px}{q} \rfloor = {\lfloor \frac{{ax} + b}{2^{k}} \rfloor = {( {{ax} + b} ) ⪢ k}}$

The rightmost notation indicates that the multiplication by a constantfraction operation reduces to a multiplication of the variable x by aconstant ‘a’ followed by an addition of a constant ‘b’, with the resultright-shifted by k places. This can be implemented very efficiently inhardware, for example through the use of a multiplication array and anadder unit. Shifting by a constant value k does not require any kind ofhardware logic: this step can be achieved simply by hardwiring thebinary output digits of the adder unit in the appropriate manner.

A binary logic circuit 605 for performing multiplication by a constantfraction in the manner of multiply-add logic 502 is shown in FIG. 6. Thelogic circuit comprises logic for performing multiplication a*x 601,logic for performing addition of constant b 602 and a shift 603. So asto maximise speed and reduce the complexity of the binary logic circuit,it is advantageous if the addition logic 602 is merged with themultiplication logic 601. For example, in preferred embodiments thebinary logic circuit is a multiplier array comprising a two or more rowsconfigured to effect multiplication by the constant integer a, with theaddition of constant b being performed at the multiplier array byintroducing the value b as an additional row in the array. It isenvisaged that at design time a reduction scheme is employed to reducethe height of the multiplication array as far as possible. This can helpto reduce the height of an array to a substantially minimum number ofrows. Shift 603 can be performed through appropriate hardwiring of thebinary digits calculated at the logic circuit to the output of the logiccircuit 605. No logic is required to implement a shift. An accumulator604 can optionally be provided at the output of the logic circuit. Theaccumulator could form part of logic circuit 605 or be providedseparately. No logic need be required to implement an accumulator.

The multiplier array 601 receives a value x which it multiplies by aconstant a by means of logic optimised for performing that specificmultiplication operation. The architecture of multiplier array 601 issuch so as to perform multiplication by the fixed constant a (e.g. ispreferably adapted for performing multiplication only by fixed constanta). It is advantageous if the array is not a generic multiplierconfigured for performing multiplication by a variable (e.g. a valuespecified at runtime). As has been discussed, this minimises thecomplexity and integrated circuit area consumed by the multiplier logic.Adder 602 performs an addition of a constant value b to the result fromthe multiplier array. Shift 603 then right-shifts the output of theadder by k places and the final output

$\frac{{ax} + b}{2^{k}}$is formed at the accumulator 604. Typically the shift would be achievedthrough suitable hardwiring of the output of the adder to the registerelements of accumulator 604.

FIG. 1 schematically illustrates the multiply, add and shift operationsperformed by an array and adder unit in order to calculate

$\frac{{ax} + b}{2^{k}}.$Each dot represents a binary digit with the constant multiplication ofthe variable ‘x’ by ‘a’ being performed by means of an array of additionoperations 101 as is known in the art. The result of the addition ofbinary constant ‘b’ at 102 is then shifted by k places as indicated by103 in order to generate the binary output 104 representing the floor of

$\frac{px}{q}.$The negative signs before rows in the multiplication array indicatethat, in the example, a canonical signed digit representation has beenemployed to decrease the Hamming weight of the binary values representedby those rows. This can often allow the multiplication array to beexpressed more efficiently in hardware and consume a smaller integratedcircuit area.

Typically there are many values of a, b and k which satisfy the aboveequation but that are difficult to identify using conventionalsimulation techniques. In order to minimise the complexity of theresulting hardware implementation, the inventor has identified that itis advantageous to select a minimum value of k. This has the effect ofminimising the value of a and hence reducing the size of themultiplication array performing the operation a*x. Once the minimumvalues of k and a have been identified, a corresponding range ofpossible values of b can be identified. This freedom in b is used toremove least significant bits from the multiplier array. Typically theoptimum value of b will correspond to a small value of b in theidentified range having a small Hamming weight. As will now be shown,this solution represents the maximally efficient expression of

$\frac{px}{q}$in terms of binary multiply-add operations.

General expressions for the minimum value of k will now be derived forgiven integers p and q. A mathematical proof that this value of krepresents the optimum solution will also be set out.

Existence and Feasibility of k

Firstly we check whether k always exists. It is always possible to findsufficiently large values for a and k such that, for any positive x:

$0 \leq ( {\frac{a}{2^{k}} - \frac{p}{q}} ) < \frac{1}{qx}$$0 \leq {{( {\frac{a}{2^{k}} - \frac{p}{q}} )x} + \frac{q - 1}{q}} < 1$$0 \leq {{( {\frac{a}{2^{k}} - \frac{p}{q}} )x} + \frac{({px}){mod}\mspace{14mu} q}{q}} < 1$$0 \leq {\frac{ax}{2^{k}} - \lfloor \frac{px}{q} \rfloor} < 1$${Hence},{\lfloor \frac{ax}{2^{k}} \rfloor = \lfloor \frac{px}{q} \rfloor}$and feasible k always exists. In fact, if k is feasible then so is k+1because:

$\lfloor \frac{{ax} + b}{2^{k}} \rfloor = \lfloor \frac{{( {2a} )x} + ( {2b} )}{2^{k + 1}} \rfloor$

The value k=0 can be readily shown to be infeasible because if k=0 then

$\lfloor \frac{px}{q} \rfloor = {{ax} + b}$

Trying x=0 and x=q yields

$\begin{matrix}{0 = b} & {p = {aq}} & {\frac{p}{q} = a}\end{matrix}$

But a is an integer and p<q so k=0 is infeasible. We can thereforeconclude that the set of feasible k is of the form[k_(min),∞)

We can further conclude that the value of a corresponding to the minimumvalue solution for k is odd. If a was even then the following would betrue and the minimum value of k would not be minimal.

$\lfloor \frac{{ax} + b}{2^{k}} \rfloor = \lfloor \frac{{( {a/2} )x} + \lfloor {b/2} \rfloor}{2^{k - 1}} \rfloor$

Hence when k=k_(min) then a is odd.

FIG. 2 illustrates the solution space for the values of α and β thatsatisfy

$\lfloor \frac{px}{q} \rfloor = \lfloor {{ax} + \beta} \rfloor$where α,β∈R. By the following lemma, the solution space shown in FIG. 2is convex.Lemma Showing the Solution Space is Convex

Consider└α₁ x+β ₁┘=└α₂ x+β ₂┘ α_(i),β_(i) ∈R

Then the following must be true└αx+β┘=└α ₁ x+β ₁┘=└α₂ x+β ₂┘whereα=(1−λ)α₁+λα₂ β=(1−λ)β₁+λβ₂ λ∈[0,1]

This result can be proved as follows:

$\begin{matrix}{{{{\alpha_{i}x} + \beta_{i}} = {c + d_{i}}}\mspace{11mu}} & {c \in Z} & {d_{i} \in \lbrack {0,1} )}\end{matrix}\mspace{20mu}$ $\begin{matrix}{\lfloor {{ax} + \beta} \rfloor = \lfloor {{( {1 - \lambda} )( {{\alpha_{1}x} + \beta_{1}} )} + {\lambda( {{\alpha_{2}x} + \beta_{2}} )}} \rfloor} \\{= {c + \lfloor {{( {1 - \lambda} )d_{1}} + {\lambda\; d_{2}}} \rfloor}} \\{= {c = \lfloor {{\alpha_{i}x} + \beta_{i}} \rfloor}}\end{matrix}$

Hence the solution space is convex.

Corollary Proving a and k are Feasible

A corollary of the above lemma is that we can prove that a and k arefeasible:

If

$\mspace{31mu}\begin{matrix}{\lfloor \frac{px}{q} \rfloor = {\lfloor {{\alpha_{1}x} + \beta_{1}} \rfloor = \lfloor {{\alpha_{2}x} + \beta_{2}} \rfloor}} & {\alpha_{i},{\beta_{i} \in R}} & {x \in Z}\end{matrix}$

Then assuming there exists

$\alpha_{1} < \frac{a}{2^{k}} < \alpha_{2}$then there must exist

$\begin{matrix}{\lambda \in \lbrack {0,1} \rbrack} & {\frac{a}{2^{k}} = {{( {1 - \lambda} )\alpha_{1}} + {\lambda\;\alpha_{2}}}}\end{matrix}$

For this λ letβ=(1−λ)β₁+λβ₂

Then

$\begin{matrix}{{\lfloor \frac{px}{q} \rfloor = {\lfloor {{\frac{a}{2^{k}}x} + \beta} \rfloor = {\lfloor \frac{{ax} + \lfloor {2^{k}\beta} \rfloor}{2^{k}} \rfloor = \lfloor \frac{{ax} + b}{2^{k}} \rfloor}}}\mspace{14mu}} & {b = \lfloor {2^{k}\beta} \rfloor}\end{matrix}$

Hence we can conclude that a and k are feasible if

$\begin{matrix}{\alpha_{i} \in R} & {\alpha_{1} < \frac{a}{2^{k}} < \alpha_{2}}\end{matrix}$

In fact, when k is a minimum then a must be unique because if not then

$\begin{matrix}{\lfloor \frac{{a_{1}x} + b_{1}}{2^{k}} \rfloor = \lfloor \frac{{a_{2}x} + b_{2}}{2^{k}} \rfloor} & {a_{1} \neq a_{2}}\end{matrix}$and by the above lemma, every real number in the following interval isfeasible

$\lbrack {\frac{a_{1}}{2^{k}},\frac{a_{2}}{2^{k}}} \rbrack$

Given a₁ and a₂ are odd then there would exist an even value of abetween them that is also feasible, which is a contradiction on k beingminimal. Hence a must be unique.

Values of a Corresponding to Minimum k

We can now identify the value of a which corresponds to the minimumvalue of k.

If the following were true

$a_{\min} > {\lceil \frac{p\; 2^{k}}{q} \rceil\mspace{14mu}{then}}$$\frac{p}{q} < {\frac{1}{2^{k}}\lceil \frac{p\; 2^{k}}{q} \rceil} < \frac{a_{\min}}{2^{k}}$

By the above corollary

$a = \lceil \frac{p\; 2^{k}}{q} \rceil$would also be feasible. But this would be a contradiction on a_(min)being unique. Hence

$\begin{matrix}{a_{\min} \leq \lceil \frac{p\; 2^{k}}{q} \rceil} & ({A1})\end{matrix}$

Similarly, if the following were true

$a_{\min} < {\lceil \frac{p\; 2^{k}}{q} \rceil\mspace{14mu}{then}}$$\frac{a_{\min}}{2^{k}} < {\frac{1}{2^{k}}\lfloor \frac{p\; 2^{k}}{q} \rfloor} < \frac{p}{q}$

And by the above corollary

$a = \lfloor \frac{p\; 2^{k}}{q} \rfloor$would also be feasible. But this would be a contradiction on a_(min)being unique. Hence

$\begin{matrix}{a_{\min} \geq \lfloor \frac{p\; 2^{k}}{q} \rfloor} & ({A2})\end{matrix}$

In conclusion, when k is at a minimum, the corresponding value of a isone of:

$\lfloor \frac{p\; 2^{k}}{q} \rfloor\mspace{14mu}{and}$$\lceil \frac{p\; 2^{k}}{q} \rceil$

In other words, the value of a when k is at a minimum is the floor of

$\frac{p\; 2^{k}}{q}$or the ceiling of

$\frac{p\; 2^{k}}{q}.$Value of b for the Case a=Floor(p2^(k)/q)

We can now identify the value of b when k is at a minimum and a is thefloor of

$\frac{p\; 2^{k}}{q}.$

Using the following identity

$\lfloor \frac{A}{B} \rfloor = \frac{A - ( {{A{mod}}\; B} )}{B}$we can identify the necessary conditions on k and b to satisfy

$a = {\lfloor \frac{p\; 2^{k}}{q} \rfloor.}$

$\begin{matrix}{{\lfloor \frac{px}{q} \rfloor = \lfloor \frac{{ax} + b}{2^{k}} \rfloor}{0 \leq {\frac{{ax} + b}{2^{k}} - \lfloor \frac{px}{q} \rfloor} < 1}{0 \leq {{( {{aq} - {p\; 2^{k}}} )x} + {2^{k}( {({px}){mod}{\mspace{14mu}\;}q} )} + {bq}} < {q\; 2^{k}}}{0 \leq {{2^{k}( {({px}){mod}{\mspace{14mu}\;}q} )} - {x( {( {p\; 2^{k}} ){mod}\mspace{20mu} q} )} + {bq}} < {q\; 2^{k}}}} & (F)\end{matrix}$

In order to find k and b that satisfy expression (F), we need to boundthe function f(x) which we define as:f(x)=2^(k)((px)mod q)−x((p2^(k))mod q)

Trying x=x_(max)=q−p⁻¹ where p⁻¹ p=1 mod q (which always exists becausep and q are coprime) and rearranging the upper bound of expression (F)we get:

$b < \frac{2^{k} + {( {q - p^{- 1}} )( {( {p\; 2^{k}} ){mod}\mspace{20mu} q} )}}{q}$which is an integer.

Now trying the substitution

$x = {x_{\min} = {q\lfloor \frac{M}{q} \rfloor}}$and rearranging the lower bound of expression (F) we get:

${\lfloor \frac{M}{q} \rfloor( {( {p\; 2^{k}} ){mod}\mspace{20mu} q} )} \leq b$

We can therefore conclude that the necessary condition on b is:

$\begin{matrix}{b\; \in \;\lbrack {{\lfloor \frac{M}{q} \rfloor( {( {p\; 2^{k}} ){mod}{\mspace{14mu}\;}q} )},{\frac{2^{k} + {( {q - p^{- 1}} )( {( {p\; 2^{k}} ){mod}\mspace{20mu} q} )}}{q} - 1}} \rbrack} & ( {B\; 1} )\end{matrix}$

This interval must be non-empty for b to exist. In other words, thefollowing must be true:

${\lfloor \frac{M}{q} \rfloor( {( {p\; 2^{k}} ){mod}\mspace{20mu} q} )} < \frac{2^{k} + {( {q - p^{- 1}} )( {( {p\; 2^{k}} ){mod}\mspace{20mu} q} )}}{q}$and hence

$\frac{2^{k}}{( {p\; 2^{k}} ){mod}\mspace{20mu} q} > {{q\lfloor \frac{M}{q} \rfloor} - q + p^{- 1}}$

These necessary conditions on k are actually sufficient because itfollows from the preceding equation and the initial condition

$M \geq {2\; q\Longrightarrow\lfloor \frac{M}{q} \rfloor } \geq 2$that

$\frac{2^{k}}{( {p\; 2^{k}} ){mod}\mspace{20mu} q} > q$

We can now identify the bounds on our function f(x). Rewriting f(x) as

$\frac{f(x)}{2^{k}} = {\underset{\underset{\in {\lbrack{0,{q - 1}}\rbrack}}{︸}}{( {({px}){mod}\mspace{20mu} q} )} - \underset{\underset{< {x\text{/}q}}{︸}}{x\frac{( {p\; 2^{k}} ){mod}\mspace{20mu} q}{2^{k}}}}$we can conclude that the maximum f(x) is attained for the smallest xsuch that(px)mod q=q−1and hencex _(max) =q−p ⁻¹   (X_MAX_(—L))

And the minimum f(x) is attained for the largest x such that(px)mod q=0and hence

$\begin{matrix}{x_{\min} = {q\lfloor \frac{M}{q} \rfloor}} & ( {X_{—}{MIN}_{—}L} )\end{matrix}$

It will be appreciated that the equations (X_MAX_L) and (X_MIN_L)represent tight bounds on x for the case

$a = {\lfloor \frac{p\; 2^{k}}{q} \rfloor.}$Value of b for the Case a=Ceiling(p2^(k)/q)

We can now identify the value of b when k is at a minimum and a is theceiling of

$\frac{p\; 2^{k}}{q}.$

Using the following identity

$\lceil \frac{A}{B} \rceil = \frac{A + ( {( {- A} ){mod}\mspace{14mu} B} )}{B}$we can identify the necessary conditions on k and b to satisfy

$a = {\lceil \frac{p\; 2^{k}}{q} \rceil.}$

$\begin{matrix}{{{\lfloor \frac{px}{q} \rfloor = \lfloor \frac{{ax} + b}{2^{k}} \rfloor}{0 \leq {\frac{{ax} + b}{2^{k}} - \lfloor \frac{px}{q} \rfloor} < 1}0 \leq {{( {{aq} - {p\; 2^{k}}} )x} + {2^{k}( {({px}){mod}\mspace{14mu} q} )} + {bq}} < {q\; 2^{k}}}{0 \leq {{2^{k}( {({px}){mod}\mspace{14mu} q} )} + {x( {( {{- p}\; 2^{k}} ){mod}\mspace{14mu} q} )} + {bq}} < {q\; 2^{k}}}} & (G)\end{matrix}$

In order to find k and b that satisfy expression (G), we need to boundthe function g(x) which we define as:g(x)=2^(k)((px)mod q)+x((−p2^(k))mod q)

Tryingx=x _(max) =M−((M+p ⁻¹)mod q)and rearranging the upper bound of expression (G) we get:

$b < \frac{2^{k} - {( {M - ( {( {M + p^{- 1}} ){mod}\mspace{14mu} q} )} )( {( {{- p}\; 2^{k}} ){mod}\mspace{14mu} q} )}}{q}$which is an integer.

Now trying the substitution x=x_(min)=0 and rearranging the lower boundof expression (G) we get:0≤b

We can therefore conclude that the necessary condition on b is:

$\begin{matrix}{b \in \lbrack {0,{\frac{2^{k} - {( {M - ( {( {M + p^{- 1}} ){mod}\mspace{14mu} q} )} )( {( {{- p}\; 2^{k}} ){mod}\mspace{14mu} q} )}}{q} - 1}} \rbrack} & ( {B\; 2} )\end{matrix}$

This interval must be non-empty for b to exist. In other words, thefollowing must be true:0<2^(k)−(M−((M+p ⁻¹)mod q))((−p2^(k))mod q)and hence

$\frac{2^{k}}{( {{- p}\; 2^{k}} ){mod}\mspace{14mu} q} > {M - ( {( {M + p^{- 1}} ){mod}\mspace{14mu} q} )}$

These necessary conditions on k are actually sufficient because itfollows from the preceding equation and the initial condition

$ {M \geq {2q}}\Rightarrow{\lfloor \frac{M}{q} \rfloor \geq 2} $that

$\frac{2^{k}}{( {{- p}\; 2^{k}} ){mod}\mspace{14mu} q} > q$

We can now identify the bounds on our function g(x). Rewriting g(x) as

$\frac{g(x)}{2^{k}} = {\underset{\underset{\in {\lbrack{0,{q - 1}}\rbrack}}{︸}}{( {({px}){mod}\; q} )} + \underset{\underset{< {x\text{/}q}}{︸}}{x\frac{( {{- p}\; 2^{k}} ){mod}\; q}{2^{k}}}}$we can conclude that the maximum g(x) is attained for the largest x suchthat(px)mod q=q−1and hencex=x _(max) =M−((M+p ⁻¹)mod q)  (X_MAX_(—U))

And the minimum g(x) is attained forx_(min)=0 (X_MIN_(—U))

It will be appreciated that the equations (X_MAX_U) and (X_MIN_U)represent tight bounds on x for the case

$a = {\lceil \frac{p\; 2^{k}}{q} \rceil.}$Optimal Parameter Selection

Using the values of a and b derived above (see equations A1, A2 and B1,B2) which represent necessary and sufficient conditions on k, we obtainthe following two sets of conditions on k, a and b which representoptimal solutions for expressing multiplication by a constant fractionin the form

$\frac{{ax} + b}{2^{k}}.$

Set 1

$k_{\min}^{-} = {\min( {{k\text{:}\frac{2^{k}}{( {p\; 2^{k}} ){mod}\mspace{14mu} q}} > {{q\lfloor \frac{M}{q} \rfloor} - q + p^{- 1}}} )}$i.e. k_(min) ⁻ is the smallest value of k that satisfies

$\frac{2^{k}}{( {p\; 2^{k}} ){mod}\mspace{14mu} q} > {{q\lfloor \frac{M}{q} \rfloor} - q + p^{- 1}}$

$a_{\min}^{-} = \lfloor \frac{p\; 2^{k_{\min}^{-}}}{q} \rfloor$$b \in \lbrack {{\lfloor \frac{M}{q} \rfloor( {( {p\; 2^{k_{\min}^{-}}} ){mod}\; q} )},{\frac{2^{k_{\min}^{-}} + {( {q - p^{- 1}} )( {( {p\; 2^{k_{\min}^{-}}} ){mod}\; q} )}}{q} - 1}} \rbrack$

Set 2

$k_{\min}^{+} = {\min( {{k\text{:}\frac{2^{k}}{( {{- p}\; 2^{k}} ){mod}\mspace{14mu} q}} > {M - ( {( {M + p^{- 1}} ){mod}\mspace{14mu} q} )}} )}$i.e. k_(min) ⁺ is the smallest value of k that satisfies

$\frac{2^{k}}{( {{- p}\; 2^{k}} ){mod}\mspace{14mu} q} > {M - ( {( {M + p^{- 1}} ){mod}\mspace{14mu} q} )}$

$a_{\min}^{+} = \lceil \frac{p\; 2^{k_{\min}^{+}}}{q} \rceil$$b_{\min}^{+} \in \lbrack {0,{\frac{2^{k_{\min}^{+}} - {( {M - ( {( {M + p^{- 1}} ){mod}\; q} )} )( {( {{- p}\; 2^{k_{\min}^{+}}} ){mod}\; q} )}}{q} - 1}} \rbrack$

The optimum solution is that set of k, a and b which correspond to thesmallest of k_(min) ⁻ and k_(min) ⁺.

The optimum solution provides the most efficient logic implementation ofa multiplier array for performing the operation round

$( \frac{px}{q} )$for all values of p and q that satisfy the initial set of constraints.This is particularly useful for values of p and q for which the optimumlogic implementation has a complex relationship to the ratio p/q.Examples of such values of p and q include the set of ratios p/q wherep>1, and the set of ratios p/q where p=1 and q!=(2^j)*((2^i)±1)) for allinteger i, j.

EXAMPLE

By way of an example, consider determining the optimum multiply-addsolution for the following multiplication by a constant fractionoperation in which p=7, q=9 and M=255 (i.e. performed to a fixed pointprecision of 8 bits).

$\frac{7x}{9} = \frac{{ax} + b}{2^{k}}$

In order to identify the optimal set of a, b and k we determine k_(min)⁻ and k_(min) ⁺:

$k_{\min} = {\min( {{k\text{:}\frac{2^{k}}{( {7*2^{k}} ){mod}\mspace{14mu} 9}} > 247} )}$$k_{\min}^{+} = {\min( {{k\text{:}\frac{2^{k}}{( {{- 7}*2^{k}} ){mod}\mspace{14mu} 9}} > 248} )}$

Trying k=7 and 8, for k_(min) ⁻ we get:

$\frac{2^{7}}{( {7*2^{7}} ){mod}\; 9} = 25.6$$\frac{2^{8}}{( {7*2^{8}} ){mod}\; 9} = 256$and for k_(min) ⁺ we get:

$\frac{2^{7}}{( {{- 7}*2^{7}} ){mod}\mspace{14mu} 9} = 32$$\frac{2^{8}}{( {{- 7}*2^{8}} ){mod}\; 9} = 32$

Hence k_(min)=8 and we use the first set of k_(min) ⁻, a_(min) ⁻ andb_(min) ⁻.

The value of a is therefore

$a_{\min}^{-} = {\lfloor \frac{7*2^{8}}{9} \rfloor = 199}$and the value of b is

${b^{-} \in \lbrack {{\lfloor \frac{255}{9} \rfloor( {( {7*2^{8}} ){mod}\mspace{14mu} 9} )},{\frac{2^{8} + {( {9 - 7^{- 1}} )( {( {7*2^{8}} ){mod}\mspace{14mu} 9} )}}{9} - 1}} \rbrack} = {\lbrack {28,28} \rbrack = 28}$

Thus, the optimal multiply-add expression of the multiplication by aconstant fraction operation is:

$\begin{matrix}{\lfloor \frac{7x}{9} \rfloor = \lfloor \frac{{199x} + 28}{2^{8}} \rfloor} & ({OPT})\end{matrix}$

FIG. 3 illustrates the advantages of implementing the multiplication bya constant fraction operation of the present example using the optimalsolution. The bottom axis of the plot in FIG. 3 represents delay in nsand the left-hand axis represents area in square micrometres. Line 301connects points in the plot representing the operational delay and areaconsumed by each of a set of logic designs generated by conventionallogic synthesis software for performing the present multiplication by aconstant fraction operation using non-constant division logic. Line 302connects points in the plot representing the operational delay and areaconsumed by each of a set of logic designs that implement presentmultiplication by a constant fraction operation according to the optimalmultiply-add operation expressed in equation (OPT) above. As can be seenfrom the plot, logic designs implemented according to the optimal designsolution taught herein are around four times smaller in terms of thearea of integrated circuit consumed, and twice as fast.

Freedom in b

In general, for the following relationship there is some freedom in thechoice of b because the result is rounded and hence there exists a rangeof solutions to the right hand side of the equation which yield the sameresult.

$\lfloor \frac{px}{q} \rfloor = \lfloor \frac{{ax} + b}{2^{k}} \rfloor$

Thus, b∈[b_(min), b_(max)] is the range which satisfies the precedingequation.

The inventor has identified that a further optimisation of amultiply-add implementation of a multiplication by a constant fractionoperation can be achieved by truncating a set of least significantbinary digits Δ from the multiplication array used to perform themultiplication of x by a (see 101 in FIG. 1). This is illustrated inFIG. 4 which shows the multiplication operation 401, the additionoperation 402, and shift 403. A set 405 of least significant binarydigits Δ can be removed from the array without modifying the result 404calculated by the array at the level of fixed point precision to whichthe multiplication by a constant fraction operation is performed. Thearea of integrated circuit consumed by the multiply-add implementationis consequently reduced.

The relationship between the bounds on the set Δ and the bounds of thepossible range of values of b are given by the following sufficientcondition:max(Δ)−min(Δ)≤b _(max) −b _(min)b∈[b_(min)+max(Δ),b_(max)+min(Δ)]  (S_(delta))

The set of multiplier array bits in the set Δ can be chosen at designtime on a trial-and-error basis with the aim of making the set Δ aslarge as possible and hence to remove as much as possible from themultiplier array. One way of achieving this is as follows.

-   -   1. As a first step, set Δ to be the least significant column of        bits in the multiplier array generated in accordance with the        optimal sets of parameters taught herein,    -   2. Test whether Δ satisfies the sufficient condition, S_(delta).    -   3. If Δ satisfies the sufficient condition, add the next least        significant column to the set Δ and re-perform step 2.    -   4. Iterate steps 2 and 3 until the sufficient condition no        longer holds, i.e. a multiplier array implementing the operation

$\frac{{ax} + b}{2^{k}}$in hardware according to an optimal set of parameters a, b and k astaught herein would no longer be guaranteed to give the true roundedvalue of

$\frac{px}{q}$that the operation is implemented to provide.

-   -   5. Choose the resulting set of bits for use as an initial guess        for Δ.

Often there will be some remaining freedom in b such that further bitscan be removed from that column of bits of the array which caused thesufficient condition to no longer hold at step 4. In order to minimisethe size of the multiplier array as far as possible, it is advantageousto at design time identify which further bits can be removed from thatcolumn of bits of the array whilst still satisfying the sufficientcondition, S_(delta). This can be done using trial and error. The choiceof these bits of A is arbitrary so long as the sufficient conditionstill holds.

Where canonical signed digit form is used in hardware, certain rows inthe multiplier array are represented as negative rows in order toimprove the efficiency of the hardware implementation of the desiredlogic operations. Typically a multiplier array configured to usecanonical signed digit form adds together all of the rows of the arraybut performs a suitable transformation on the negative rows so as toeffect the correct logical operation.

For example, a negative row can have the formula −x*2^(i). Since it isknown that the array is going to sum to a positive K bit binary number(e.g. a large enough binary number such that it can store any outputfrom the array), we can add 2^(k) to any negative row as this will notaffect any of the K least significant bits, which include the outputbits of the array. Thus, the above formula becomes2^(k−) x*2^(i)=(not(x)+1)*2^(i)where not(x) is the logical negation of x if x were interpreted as anK−i bit number (this may involve the appending of many 0s to the frontof x). When any appended 0s are logically negated they become 1s. Theseleading 1s are what is called signed extending x. The logical negationcomes from the positive equationnot(t)+t=2^(n)−1assuming t is an n-bit unsigned binary number.

The constant 1s as well as the constant addition of 2^(i) can beabsorbed into the constant b, leaving the negative row as:not(x)*2^(i)where the not is applied just to the length of x.

In this manner, arithmetic negation can correspond to logical bitwisenegation of x (with some adaption to the value of b).

Once a best guess for Δ has been established, the maximum and minimumvalues of the set Δ can be calculated as follows where canonical signeddigit form is used. Each row in the multiplication array is a copy ofthe variable x, left-shifted by i bits where i is the position of therespective ith bit of fixed integer a having a value of +1 or −1 (sincecanonical signed digit form is being used in hardware). For theidentified set of least significant bits Δ, we can identify all thetimes the bit x[0] appears, the bit x[1] appears, x[2] etc. Each bitx[j] might appear in a negative or positive row of the multiplier array.

In order to calculate a lower bound for the minimum of Δ:

-   -   where the most significant (i.e. left-most) occurrence of x[j]        appears in a negative row, we choose to set all those positions        x[j]=1;    -   where the most significant (i.e. left-most) occurrence of x[j]        appears in a positive row, we choose to set all those positions        x[j]=0.

In order to calculate an upper bound for the maximum of Δ:

-   -   where the most significant (i.e. left-most) occurrence of x[j]        appears in a negative row, we choose to set all those positions        x[j]=0;    -   where the most significant (i.e. left-most) occurrence of x[j]        appears in a positive row, we choose to set all those positions        x[j]=1.

By following this procedure at design time for all the bit positions inx which appear in delta, we obtain the minimum and maximum bounds for Δ.

The new range of b can be calculated from the maximum and minimum valuesof Δ using the sufficient condition S_(delta) set out above. A sensiblevalue of b is the value in that range having the minimum Hamming weight.

Method of IC Design

The optimal solutions for a multiply-add implementation of amultiplication by a constant fraction operation which are describedherein can be determined by suitable software. Typically, integratedcircuits are initially designed using software (e.g. Synopsis DesignCompiler) that generates a logical abstraction of the desired integratedcircuit. Such an abstraction is generally termed register-transfer levelor RTL. Once the logical operation of the integrated circuit has beendefined, this can be used by synthesis software (e.g. Synopsis ICCompiler) to create representations of the physical integrated circuit.Such representations can be defined in high level hardware descriptionlanguages, for example Verilog or VHDL and, ultimately, according to agate-level description of the integrated circuit.

Logic for performing multiplication by a constant fraction can bereadily introduced into an integrated circuit at design time. However,the design software used for designing integrated circuits will almostinvariably provide the functionality using logic for performing genericdivision—i.e. logic for performing division by a divisor specified atruntime. Such logic is complex and consumes a significant area ofintegrated circuit. It is therefore preferable that, where logic forperforming multiplication by a constant fraction is required, designsoftware is configured to use logic optimised for performingmultiplication by a constant fraction by means of a multiply-addoperation of the form

$\frac{{ax} + b}{2^{k}}.$The optimal solution for such an operation is described herein.

It is advantageous if software for designing an integrated circuit isconfigured to, on a multiplication by a constant fraction operationbeing specified by the designer, implement the operation in accordancewith the design principles described herein. This could be byintroducing into the integrated circuit design RTL defining amultiply-add operation of the form

$\frac{{ax} + b}{2^{k}}$rather than a generic division function. The values of a, b and k can bechosen according to the optimal parameter selections described above.The software could implement multiplication by a constant fraction usinga multiplier array. Preferably the software would be further configuredto remove a set of Δ least significant bits from the multiplier array,as taught herein. The design of an integrated circuit can be effectedaccording to the rules embodied in the design software at a dataprocessing device executing the design software (such as a workstationor server).

A method of deriving a hardware representation of a binary logic circuitin accordance with the principles set out herein is illustrated in theflowchart of FIG. 7. At 701, a multiplication by a constant fractionoperation

$\frac{px}{q}$to be expressed in the efficient form

$\frac{{ax} + b}{2^{k}}$is received. At 702, the appropriate smallest value of k is thendetermined from the minimum values of k that satisfy set 1 or 2 of theoptimal parameter sets described above. The resulting value of k is thenused at 703 to determine the appropriate values of a and b—i.e. thevalues of a and b from the corresponding set of the selected k are used.Once appropriate values of a, b and k have been identified, at 704 ahardware representation of a binary logic circuit in the form

$\frac{{ax} + b}{2^{k}}$is derived in the desired format. For example, the hardwarerepresentation could be a register-transfer level (RTL) representation,a high-level circuit representations such as Verilog or VHDL, or alower-level representations such as OASIS or GDSII. The hardwarerepresentation of the binary logic circuit can be provided (typically aspart of a larger-scale chip design) for fabrication into an integratedcircuit. For example, a low-level representation of an IC could beprovided directly to a foundry for fabrication of the specifiedintegrated circuit, or RTL could be provided to an intermediate chipdesigner who would themselves design a low-level representation of an ICfrom the RTL for provision to a foundry.

The method of FIG. 7 could be implemented in program code, such as RTLdesign software. For example, on a user of the software specifying amultiplication by a constant fraction operation, the RTL design softwarecould be configured to implement the operation using RTL definingmultiply-add logic in the form

$\frac{{ax} + b}{2^{k}},$where a, b and k take the values described herein.General Optimal Solution

The above-described optimal solutions for a multiply-add implementationof a multiplication by a constant fraction operation can be extended tothe following more general operation.

${\lfloor \frac{{p*x} + r}{q} \rfloor = ( {{a*x} + b} )}\operatorname{>>}k$where x is in the range [A, B] and r is a positive integer.

The two sets of k, a, b which represent the optimal solutions in thismore general case are as follows. These solutions can be derived byfollowing the same steps set out above for the more limited case inwhich the optimal solution to

$\frac{px}{q}$is sought and with the same constraints, but with x being in the range[A, B] and the constraint M≥2q being replaced by (B−A)≥2q.

Set 1

$\mspace{76mu}{k^{-} = {\min( {{k\text{:}\frac{2^{k}}{( {p\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q}} > {\beta_{\min}^{-} - \beta_{\max}^{-}}} )}}$$\mspace{76mu}{a^{-} = \lfloor \frac{p\; 2^{k}}{q} \rfloor}$$b^{-} \in \lbrack {\frac{{r\; 2^{k}} + {\beta_{\min}^{-}*( {p\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q}}{q},{\frac{{2^{k}( {r + 1} )} + {\beta_{\max}^{-}*( {p\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q}}{q} - 1}} \rbrack$     where      β_(max)⁻ = A + (−A − P_(q)⁻¹(r + 1))  mod  q     β_(min)⁻ = B − (B + r * P_(q)⁻¹)  mod  q

Set 2

$\mspace{76mu}{k^{+} = {\min( {{k\text{:}\frac{2^{k}}{( {{- p}\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q}} > {\beta_{\max}^{+} - \beta_{\min}^{+}}} )}}$$\mspace{76mu}{a^{+} = \lceil \frac{p\; 2^{k}}{q} \rceil}$$b^{+} \in {\lbrack {\frac{{r\; 2^{k}} - {\beta_{\min}^{+}*( {{- p}\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q}}{q},{\frac{{2^{k}( {r + 1} )} - {\beta_{\max}^{+}*( {{- p}\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q}}{q} - 1}} \rbrack\mspace{76mu}{where}}$     β_(max)⁺ = B − (B + P_(q)⁻¹(r + 1))  mod  q     β_(min)⁺ = A + (−A − r * P_(q)⁻¹)  mod  q

Again, the smallest of k⁻ and k⁺ and its associated a and b valuesrepresent the optimal solution. In the case that A is negative, x can bea signed number and the optimised multiplier array for performing thedesired multiplication by a constant fraction is configured to acceptand return signed numbers.

The fixed point filter of FIG. 5 and the frame processor of FIG. 6 areshown as comprising a number of functional blocks. This is schematiconly and is not intended to define a strict division between differentlogic elements of an integrated circuit. Each functional block can beprovided in any suitable manner.

The terms software and computer readable program code as used hereinincludes executable code for processors (e.g. CPUs and/or GPUs),firmware, bytecode, programming language code such as C or OpenCL, andmodules for reconfigurable logic devices such as FPGAs. Machine-readablecode includes software and code for defining hardware representations ofintegrated circuits at any level, including at register transfer level(RTL), at high-level circuit representations such as Verilog or VHDL,and lower-level representations such as OASIS and GDSII.

The algorithms and methods described herein could be performed by one ormore physical processing units executing software that causes theunit(s) to perform the algorithms/methods. The or each physicalprocessing unit could be any suitable processor, such as a CPU or GPU(or a core thereof), or fixed function or programmable hardware. Thesoftware could be stored in non-transitory form at a machine readablemedium such as an integrated circuit memory, or optical or magneticstorage. A machine readable medium might comprise several memories, suchas on-chip memories, computer working memories, and non-volatile storagedevices.

The applicant hereby discloses in isolation each individual featuredescribed herein and any combination of two or more such features, tothe extent that such features or combinations are capable of beingcarried out based on the present specification as a whole in the lightof the common general knowledge of a person skilled in the art,irrespective of whether such features or combinations of features solveany problems disclosed herein, and without limitation to the scope ofthe claims. The applicant indicates that aspects of the presentinvention may consist of any such individual feature or combination offeatures. In view of the foregoing description it will be evident to aperson skilled in the art that various modifications may be made withinthe scope of the invention.

What is claimed is:
 1. A binary logic circuit configured to determine,for an input value x, a rounded value of $\frac{{p*x} + r}{q}$ byimplementing me operation $\frac{{ax} + b}{2^{k}},$ where p and q arecoprime constant integers with p<q and q≠2^(i), r is a positive integer,i is an integer, and input value x is an integer variable betweenintegers A and B where (B−A)≥2q, where a and b are predetermined fixedintegers, and k is the smallest integer that satisfies either:$\begin{matrix}{{{\frac{2^{k}}{( {p\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q} > {\beta_{\min}^{-} - \beta_{\max}^{-}}}{where},{\beta_{\max}^{-} = {A + {( {{- A} - {p_{q}^{- 1}( {r + 1} )}} )\mspace{14mu}{mod}\mspace{14mu} q}}}}{\beta_{\min}^{-} = {B - {( {B + {r*p_{q}^{- 1}}} )\mspace{14mu}{mod}\mspace{14mu} q}}}{{or}\text{:}}} & (a) \\{{{\frac{2^{k}}{( {{- p}\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q} > {\beta_{\max}^{+} - \beta_{\min}^{+}}}{where},{\beta_{\max}^{+} = {B - {( {B + {p_{q}^{- 1}( {r + 1} )}} )\mspace{14mu}{mod}\mspace{14mu} q}}}}{\beta_{\min}^{+} = {A + {( {{- A} - {r*p_{q}^{-}}} )\mspace{14mu}{mod}\mspace{14mu} q}}}} & (b)\end{matrix}$ wherein the binary logic circuit comprises: multiplicationand addition logic having an input to receive x and configured inhardware to: perform the multiplication of x by the predetermined fixedinteger a; be incapable of performing multiplication of x by a variablefactor; and perform the addition of the predetermined fixed integer b;wherein, in dependence on the values of p, q and r: if (a) is satisfiedby a smaller integer k than (b), then a is predetermined to be aninteger given by $\lfloor \frac{p\; 2^{k}}{q} \rfloor$  and bis predetermined to be an integer in the range$\lbrack {\frac{{r\; 2^{k}} + {\beta_{\min}^{-}*( {p\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q}}{q},{\frac{{2^{k}( {r + 1} )} + {\beta_{\max}^{-}*( {p\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q}}{q} - 1}} \rbrack;$ and if (b) is satisfied by a smaller integer k than (a), then a ispredetermined to be an integer given by$\lceil \frac{p\; 2^{k}}{q} \rceil$  and b is predeterminedto be an integer in the range$\lbrack {\frac{{r\; 2^{k}} - {\beta_{\min}^{+}*( {{- p}\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q}}{q},{\frac{{2^{k}( {r + 1} )} - {\beta_{\max}^{+}*( {{- p}\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q}}{q} - 1}} \rbrack.$2. A binary logic circuit as claimed in claim 1, the binary logiccircuit being a binary multiplier array comprising the multiplicationand addition logic, the binary multiplier array having a plurality ofrows, a first subset of the plurality of rows being configured toperform the multiplication by the fixed integer a, a second subset ofthe plurality of rows being configured to perform the addition of b, andsaid rounded value being the output of the multiplier arrayright-shifted by k binary digits.
 3. A binary logic circuit as claimedin claim 2, the first subset of the plurality of rows of the binarymultiplier array being a substantially minimum number of rows requiredto implement the multiplication of x by fixed integer a.
 4. A binarylogic circuit as claimed in claim 2, the second subset of the pluralityof rows of the binary multiplier array being a single row arranged toperform the addition of fixed integer b.
 5. A binary logic circuit asclaimed in claim 2, the plurality of rows of the multiplier array beingarranged such that the representations of the integer variable x atthose rows are collectively truncated by a set of Δ least significantdigits, the set of Δ least significant digits being substantially thelargest number of least significant digits that can be discarded withoutcausing the multiplier array to deviate from the true rounded value of$\frac{{px} + r}{q}$ for any x between A and B.
 6. A binary logiccircuit as claimed in claim 5, wherein the fixed integer b is theinteger having the smallest Hamming weight which satisfies saidoperation for all x.
 7. A binary logic circuit as claimed in claim 6,wherein, in the case that (a) is satisfied by a smaller integer k than(b), if there is more than one value of b having the same smallestHamming weight, the fixed integer b is the smallest value of b.
 8. Abinary logic circuit as claimed in claim 2, the multiplier array beingunable to perform multiplication by a variable.
 9. A binary logiccircuit as claimed in claim 1, the multiplication and addition logicmaking use of a canonical signed digit representation.
 10. A binarylogic circuit as claimed in claim 1, the binary logic circuit beingconfigured to determine the rounded value of $\frac{{px} + r}{q}$according to any one of the following rounding schemes: round towardszero (RTZ), round towards negative infinity (RTN), round towardspositive infinity (RTP), and round towards nearest with ties to upper(RTU).
 11. A machine readable storage medium having encoded thereonnon-transitory machine readable code for generating a binary logiccircuit according to claim
 1. 12. A fixed point filter comprising one ormore binary logic circuits configured as claimed in claim
 1. 13. Amethod of deriving a hardware representation of a binary logic circuitconfigured to determine, for an input value x, a rounded value of$\frac{{p*x} + r}{q}$ by implementing the operation$\frac{{ax} + b}{2^{k}},$ where p and q are coprime constant integerswith p<q and q≠2^(i), r is a positive integer, i is an integer, inputvalue x is an integer variable between integers A and B where (B−A)≥2q,and a, b and k are fixed integers, the method comprising: determining,in dependence on the values of p, q and r, the integer k as the smallestinteger that satisfies either: $\begin{matrix}{{{\frac{2^{k}}{( {p\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q} > {\beta_{\min}^{-} - \beta_{\max}^{-}}}{where},{\beta_{\max}^{-} = {A + {( {{- A} - {p_{q}^{- 1}( {r + 1} )}} )\mspace{14mu}{mod}\mspace{14mu} q}}}}{\beta_{\min}^{-} = {B - {( {B + {r*p_{q}^{- 1}}} )\mspace{14mu}{mod}\mspace{14mu} q}}}{{or}\text{:}}} & (a) \\{{{\frac{2^{k}}{( {{- p}\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q} > {\beta_{\max}^{+} - \beta_{\min}^{+}}}{where},{\beta_{\max}^{+} = {B - {( {B + {p_{q}^{- 1}( {r + 1} )}} )\mspace{14mu}{mod}\mspace{14mu} q}}}}{\beta_{\min}^{+} = {A + {( {{- A} - {r*p_{q}^{- 1}}} )\mspace{14mu}{mod}\mspace{14mu} q}}}} & (b)\end{matrix}$ determining fixed integers a and b such that: if (a) issatisfied by a smaller integer k than (b), calculating a as the integergiven by $\lfloor \frac{p\; 2^{k}}{q} \rfloor$  and selectingb from the set of one or more integers in the range$\lbrack {\frac{{r\; 2^{k}} + {\beta_{\min}^{-}*( {p\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q}}{q},{\frac{{2^{k}( {r + 1} )} + {\beta_{\max}^{-}*( {p\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q}}{q} - 1}} \rbrack,$ and if (b) is satisfied by a smaller integer k than (a), calculating aas the integer given by $\lceil \frac{p\; 2^{k}}{q} \rceil$ and selecting b from the set of one or more integers in the range$\lbrack {\frac{{r\; 2^{k}} - {\beta_{\min}^{+}*( {{- p}\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q}}{q},{\frac{{2^{k}( {r + 1} )} - {\beta_{\max}^{+}*( {{- p}\; 2^{k}} )\mspace{14mu}{mod}\mspace{14mu} q}}{q} - 1}} \rbrack;$and deriving, using the determined fixed integers, a, b and k, ahardware representation for a binary logic circuit configured toimplement the operation $\frac{{ax} + b}{2^{k}}$  by usingmultiplication and addition logic configured in hardware to: performmultiplication of x by the predetermined fixed integer a; be incapableof performing multiplication of x by a variable factor; and perform theaddition of the predetermined fixed integer b.
 14. A method as claimedin claim 13, wherein deriving the hardware representation for the binarylogic circuit comprises implementing said operation using a binarymultiplier array comprising the multiplication and addition logic, thebinary multiplier array having a plurality of rows, a first subset ofthe plurality of rows being configured to perform multiplication by thefixed integer a, a second subset of the plurality of rows beingconfigured to perform the addition of b, and the rounded value being theoutput of the multiplier array right-shifted by k binary digits.
 15. Amethod as claimed in claim 14, further comprising modifying saidhardware representation by truncating a set of Δ least significantdigits from the plurality of rows, the set of Δ least significant digitsbeing substantially the largest set of least significant digits that canbe discarded without causing the operation implemented by the binarylogic circuit to deviate from the true rounded value of$\frac{{px} + r}{q}$ for any x between A and B.
 16. A method as claimedin claim 15, wherein the fixed integer b is selected to be the integerhaving the smallest Hamming weight that satisfies the truncated hardwarerepresentation for the binary logic circuit.
 17. A method as claimed inclaim 13, wherein the hardware representation is RTL, a hardwaredescription language, or a gate-level description language.
 18. Acomputer readable storage medium having encoded thereon non-transitorycomputer readable program code for generating a hardware representationaccording to the method of claim
 13. 19. A method of manufacturing anintegrated circuit, the method comprising fabricating a binary logiccircuit, derived according to the method as claimed in claim
 13. 20. Anintegrated circuit manufactured according to the method of claim 19.